In non-packet based radio receivers, such as WCDMA receivers, gain control must be performed while receiving signals. Accordingly, it is desirable to minimize disruption to the received signal due to gain control. If DC offsets are present and the gain control is performed digitally, that is if gain is achieved using switches, the rapid change in gain causes a step response in the received signal. The step response de-sensitizes the receiver and may cause the receiver to lose the received signal until the receiver has settled.
The step response caused by DC offsets and digital gain control can be eliminated by rejecting the DC offset prior to amplification. One method of rejecting the DC offset is to couple the received signal to the input of an amplifier using a capacitor. However, in order to achieve a sufficiently low cut-off frequency for a high-pass filter, the time-constants required are large. Thus, the capacitor must also be large. The large capacitor causes the receiver to have a longer turn-on time because sufficient charge must be delivered to the capacitor to reach the required quiescent bias voltage. If it is desirable to implement the capacitor on a semiconductor die, the large capacitance also requires a large die area, thereby increasing cost. Thus, there remains a need for an amplifier that provides digital gain control, eliminates step responses in the output signal due to DC offsets in the input signal, and that has a short turn-on time.